1. Field of the Invention
This invention relates to the field of computer aided design for digital circuits, and particularly to analyzing and debugging digital circuits constructed from HDL source text using logic or behavioral synthesis.
2. Statement of the Related Art
A digital circuit designer needs to ensure that the digital circuit performs the correct function subject to many design constraints. For example, the digital circuit should perform the correct computation in the proper amount of time. The area that the digital circuit occupies on a semiconductor die should remain within certain bounds. The power that the digital circuit consumes while operating should also remain within specified bounds. To be economically manufacturable, the digital circuit should be testable. An economically useful digital circuit should not take too long to design, manufacture, test or use.
The digital circuit design process typically involves translating the designer's sometimes incipient thoughts about the function and constraints into the tooling necessary to produce a working digital circuit. For example, producing a full-custom semiconductor chip requires producing masks that define the deposition of chemicals into a substrate as well as producing test patterns that exercise the final product. As another example of tooling, producing a field programmable gate array requires generating the bit pattern to be downloaded into the chip to specify the configuration of the architecture. Computer Aided Design (CAD) tools facilitate the iterative translation of the designer's developing thoughts into the tooling required to produce a working digital circuit that satisfies the design constraints. The process of iteratively adjusting a design to meet its constraints is called debugging. The process of identifying various properties of different parts of a digital circuit is called analysis. In order to debug a digital circuit, the designer must first analyze the circuit to ascertain where problems occur.
The typical historical model of the digital design process using conventional CAD tools for a semiconductor chip is as follows. The designer first conceives of a particular function to implement, as well as constraints such as timing or area that the implementation must meet. Next, historically, the designer mentally transforms the desired function into a high level generic technology circuit consisting of components such as gates, adders, registers and RAMs.
The designer then chooses a technology provided by a semiconductor vendor from which the circuit components will be chosen. The process of choosing circuit components from a specific technology is called mapping; mapping creates a mapped circuit. To map a circuit, the designer draws a schematic of a mapped circuit that implements the desired function with a CAD schematic capture tool. The mapped circuit includes parts from a software representation of a specific technology library which is supplied by a silicon vendor. The schematic shows how more primitive functional elements, such as gates or transistors, connect together to form more sophisticated functions such as arithmetic logic units. In addition, modern schematic capture tools allow the designer to divide the design hierarchically into interconnected pieces, and then allow the user to specify the details of each of the pieces separately. For example, Design Architect by Mentor Graphics of Wilsonville, Oreg. provides these schematic capture functions.
Conventional CAD tools, such as those indicated above, can then take the connections in the schematic and other information to evaluate the mapped circuit and to specify the tooling necessary to construct the circuit. Such tools evaluate the mapped circuit in many ways. For example, commercial CAD tools often have a simulator that predicts the response of the mapped circuit to designer specified input patterns. QuickSim II by Mentor Graphics of Wilsonville, Oreg. is a commonly used simulator. Another common CAD tool is a path delay analyzer that identifies the longest timing path in a mapped circuit design. DesignTime by Synopsys, Inc. of Mountain View, Calif. is a tool that provides path delay analysis.
There are conventional CAD tools that have the ability to generate the geometric layout of the digital circuit with layout tools. Cell3 Ensemble by Cadence of San Jose, Calif. is an example of this type of tool. Layout tools are required to produce masks to make a semiconductor chip.
There are conventional CAD tools that have the ability to check that the digital circuit meets the design rules, and to identify the location of any errors to the designer. Design rules help ensure that the specified digital circuit will operate once manufactured.
There are conventional CAD tools that are used to determine how testable a mapped circuit is, and to generate test patterns automatically. Showing the designer the parts of the mapped circuit that are not testable allows the designer to make modifications that will increase the probability of making a successful chip or circuit. Generating test patterns automatically allows for more thorough testing of the digital circuit immediately after manufacturing.
As described above, the concept of analyzing a mapped circuit design historically refers to the process by which a digital circuit designer specified a particular implementation with a schematic capture tool, and then used various circuit evaluation tools to verify that the implementation did what the digital circuit designer wanted. For example, the designer would use a simulator to determine if the mapped circuit produced appropriate outputs from specified inputs. The designer could use the path delay analyzer to determine whether the current design was fast enough to meet the timing constraints. The layout tools could inform the designer whether the design meets the area constraints.
When a particular design did not meet the designer's constraints, the designer then modified the design. For example, if the mapped circuit was too slow, the designer identified the part of the mapped circuit that was too slow, and revised it to increase performance. If the mapped circuit was too large, then the designer revised the mapped circuit to use fewer or smaller components. If the mapped circuit did not behave as required, the designer changed the components and the interconnections to produce the correct function. Because the conventional CAD tools began the analysis with the mapped circuit, the timing or area problems could be readily identified to the designer. Because the designer specified the structure of the mapped circuit, the designer could thoughtfully make adjustments. However, the CAD tools were limited in their ability to identify functional problems because the designer had mentally performed the transformation from desired function to mapped circuit. In other words the CAD tools included structural information about the digital circuit, but did not include data concerning the high level functionality of the digital circuit.
Logic synthesis was developed to provide the designer with an automatic mechanism to translate a hardware description language (HDL) description of a desired function to a structural description of a digital circuit that performed the desired function. Logic synthesis begins with the designer describing the desired function using VHDL, Verilog, or any other logic synthesis source language, to specify the behavior. This allows the designer to specify the digital circuit at a higher level, and allows the CAD tools to assist the designer in defining the functionality of the digital circuit. A software translator then converts that description into generic technology structures that directly correspond statement by statement with the designer's description.
In logic synthesis, translation is followed by logic optimization. Optimization involves two steps. First, it replaces the directly translated structure with a functionally equivalent, yet improved structure. Second, the optimization process includes an optional step called mapping the design. Mapping replaces the generic technology structures with structures from a specific technology library. Technology libraries are provided by silicon vendors to specify the types of parts which the vendor can manufacture. Technology libraries include specific information regarding the functionality and physical characteristics such as area and delay of gates which can be built by the silicon vendor. Technology libraries are designed to work with synthesis systems. A synthesis system can use a technology library to choose available gates from which the silicon vendor can fabricate the digital circuit.
Unfortunately, the transformations performed by the logic optimizer usually modify the structure that was present in the pre-optimization circuit. This results in a mapped circuit that is not easily recognized by the designer. The fact that the designer generally can not readily recognize the original function performed by the mapped circuit makes analyzing optimized mapped circuits difficult. Conventional evaluation tools can determine the timing or area problems in the mapped circuit, but the designer often can not relate those problems easily to the HDL source specification. Theoretically, the designer could manually determine what part of the HDL specification caused the problem. With that insight, the designer could make the desired changes at the HDL specification, and resynthesize the entire digital circuit. If the designer's problem occurred in a part of the mapped circuit that passed through the optimizer with few changes, manual backtracking might work. However, the optimization process generally makes many changes, making it either difficult or impossible to backtrack because many points in the original generic technology circuit do not exist in the mapped circuit.
Furthermore, the level of circuit improvement produced by logic optimization is not consistent. Due to the computational complexity of the optimization problem, optimizers must rely upon approximate, rather than optimal algorithms. The effect of the optimizer is, in some senses, random, because a slightly different initial circuit can significantly affect the choices that the optimizer makes. Therefore, it is impossible to predict consistently the percentage improvement that the optimizer will deliver. A small change in the HDL specification may result not only in a substantially different mapped circuit, but may also result in a mapped circuit which is substantially larger or slower.
As one possible solution, the designer can directly modify the mapped circuit produced by the synthesis software. However, this does not allow the designer to resynthesize the design from the HDL specification because the designer's logic changes is overwritten by subsequent translation and optimization steps. This reduces the value gained by using the synthesis approach to design.
One prior system which attempted to link HDL source text to generic technology and mapped circuits was "Source to Gates" which is included as a feature of Design Analyzer by Synopsys Inc., located in Mountain View, Calif. Source to Gates allowed the designer to trace between HDL source and schematics. Source to Gates did not prove useful because its ability to trace post synthesis mapped structures to the HDL source was limited to optimization invariant circuit structures that were present in the HDL source. Although Source to Gates did allow the designer to trace between schematics of the generic technology circuit and the HDL source, this feature was not particularly useful because it required viewing of the generic technology circuit which was not directly meaningful to the designer and no analysis link to the source was provided.
An additional limitation of Source to Gates is that it stores text location in terms of row and column numbers. Thus, when tracing from a schematic to HDL text, Source to Gates only hilights the first character of the appropriate parse node. There is no indication of the range of the parse node. There are two modes in Source to Gates when tracing from text to the schematic. Exact match mode forces the user to place the cursor on the first character of a parse node in order to enable tracing to the schematic. Closest match mode searches forwards and backwards in the text to find the closest traceable character. In this mode, the user does not know exactly what will be traced.
Another method for minimizing the backtracking problem in the analysis of an optimized mapped circuit is to partition the design into hierarchical components, and translate and optimize the smaller pieces. Because the translation and optimization tools generally do not traverse primary inputs and outputs, the HDL description can be correlated with a particular resulting mapped sub-circuit, thus reducing the size of the backtracking problem. However, repartitioning has the disadvantage that the designer may have to rewrite functionally correct, but nonetheless problematic, HDL source code to isolate the troublesome parts of the mapped circuit. In addition, this approach will greatly limit the optimizer's ability to reduce the area and increase the speed of the resulting circuits because the optimizer will be constrained by the designer's partition.
In addition, it is possible for a designer to be mislead by the results obtained by analysis by partitioning. The designer's bug in the circuit might be that it is too slow or too big. Partitioning the HDL source to locate the cause will likely result in a different circuit than the unpartitioned source. Therefore, the problem that the designer is chasing may be affected by the analysis process itself.
Conventionally, using a synthesizer to transform an HDL source specification into a mapped circuit can also cause substantial computational problems if one needs to incorporate minor changes into a design late in the design process. For example, a designer could have the design fairly close to completion when the designer discovers the need to make a small functional change, such as inverting a particular signal. Intuitively, one would expect that such a small change would require only a small change in the digital circuit all the way to the layout level. However, it is quite possible that, with conventional translation and optimization tools, a small change could require substantial changes in the mapped circuit and the circuit layout. With current tools, a designer can often limit this kind of problem by partitioning the design into smaller pieces and thus limiting the effect to the directly implicated pieces. However, as described previously, inappropriate or unduly narrow partitioning can limit the ability of the optimization tools to construct a mapped circuit which meets the design constraints.